#include "ddrc_init.h"
#include "lpddr3_ctl_timing.h"
#include "lpddr3_phy_timing.h"
#include "lpddr4_ctl_timing.h"
#include "lpddr4_phy_timing.h"


DDRC_DMC_DTMG_T dmc_tmg_lp3[]=
{
	{
		DMC_LP3_256_MR1,
		DMC_LP3_256_MR2,
		DMC_LP3_256_MR3,
		DMC_LP3_256_MR22,
		DMC_LP3_256_DTMG0,
		DMC_LP3_256_DTMG1,
		DMC_LP3_256_DTMG2,
		DMC_LP3_256_DTMG3,
		DMC_LP3_256_DTMG4,
		DMC_LP3_256_DTMG5,
		DMC_LP3_256_DTMG6,
		DMC_LP3_256_DTMG7,
		DMC_LP3_256_DTMG8,
		DMC_LP3_256_DTMG9,
		DMC_LP3_256_DTMG10,
		DMC_LP3_256_DTMG11,
		DMC_LP3_256_DTMG12,
		DMC_LP3_256_DTMG13,
		DMC_LP3_256_DTMG14,
		DMC_LP3_256_DTMG15,
		DMC_LP3_256_DTMG16,
		DMC_LP3_256_DTMG17,
		DMC_LP3_256_DTMG18,
		DMC_LP3_256_DTMG19,
	},
	{
		DMC_LP3_384_MR1,
		DMC_LP3_384_MR2,
		DMC_LP3_384_MR3,
		DMC_LP3_384_MR22,
		DMC_LP3_384_DTMG0,
		DMC_LP3_384_DTMG1,
		DMC_LP3_384_DTMG2,
		DMC_LP3_384_DTMG3,
		DMC_LP3_384_DTMG4,
		DMC_LP3_384_DTMG5,
		DMC_LP3_384_DTMG6,
		DMC_LP3_384_DTMG7,
		DMC_LP3_384_DTMG8,
		DMC_LP3_384_DTMG9,
		DMC_LP3_384_DTMG10,
		DMC_LP3_384_DTMG11,
		DMC_LP3_384_DTMG12,
		DMC_LP3_384_DTMG13,
		DMC_LP3_384_DTMG14,
		DMC_LP3_384_DTMG15,
		DMC_LP3_384_DTMG16,
		DMC_LP3_384_DTMG17,
		DMC_LP3_384_DTMG18,
		DMC_LP3_384_DTMG19,
	},
	{
		DMC_LP3_512_MR1,
		DMC_LP3_512_MR2,
		DMC_LP3_512_MR3,
		DMC_LP3_512_MR22,
		DMC_LP3_512_DTMG0,
		DMC_LP3_512_DTMG1,
		DMC_LP3_512_DTMG2,
		DMC_LP3_512_DTMG3,
		DMC_LP3_512_DTMG4,
		DMC_LP3_512_DTMG5,
		DMC_LP3_512_DTMG6,
		DMC_LP3_512_DTMG7,
		DMC_LP3_512_DTMG8,
		DMC_LP3_512_DTMG9,
		DMC_LP3_512_DTMG10,
		DMC_LP3_512_DTMG11,
		DMC_LP3_512_DTMG12,
		DMC_LP3_512_DTMG13,
		DMC_LP3_512_DTMG14,
		DMC_LP3_512_DTMG15,
		DMC_LP3_512_DTMG16,
		DMC_LP3_512_DTMG17,
		DMC_LP3_512_DTMG18,
		DMC_LP3_512_DTMG19,
	},
	{
		DMC_LP3_622_MR1,
		DMC_LP3_622_MR2,
		DMC_LP3_622_MR3,
		DMC_LP3_622_MR22,
		DMC_LP3_622_DTMG0,
		DMC_LP3_622_DTMG1,
		DMC_LP3_622_DTMG2,
		DMC_LP3_622_DTMG3,
		DMC_LP3_622_DTMG4,
		DMC_LP3_622_DTMG5,
		DMC_LP3_622_DTMG6,
		DMC_LP3_622_DTMG7,
		DMC_LP3_622_DTMG8,
		DMC_LP3_622_DTMG9,
		DMC_LP3_622_DTMG10,
		DMC_LP3_622_DTMG11,
		DMC_LP3_622_DTMG12,
		DMC_LP3_622_DTMG13,
		DMC_LP3_622_DTMG14,
		DMC_LP3_622_DTMG15,
		DMC_LP3_622_DTMG16,
		DMC_LP3_622_DTMG17,
		DMC_LP3_622_DTMG18,
		DMC_LP3_622_DTMG19,
	},
	{
		DMC_LP3_768_MR1,
		DMC_LP3_768_MR2,
		DMC_LP3_768_MR3,
		DMC_LP3_768_MR22,
		DMC_LP3_768_DTMG0,
		DMC_LP3_768_DTMG1,
		DMC_LP3_768_DTMG2,
		DMC_LP3_768_DTMG3,
		DMC_LP3_768_DTMG4,
		DMC_LP3_768_DTMG5,
		DMC_LP3_768_DTMG6,
		DMC_LP3_768_DTMG7,
		DMC_LP3_768_DTMG8,
		DMC_LP3_768_DTMG9,
		DMC_LP3_768_DTMG10,
		DMC_LP3_768_DTMG11,
		DMC_LP3_768_DTMG12,
		DMC_LP3_768_DTMG13,
		DMC_LP3_768_DTMG14,
		DMC_LP3_768_DTMG15,
		DMC_LP3_768_DTMG16,
		DMC_LP3_768_DTMG17,
		DMC_LP3_768_DTMG18,
		DMC_LP3_768_DTMG19,
	},
	{
		DMC_LP3_933_MR1,
		DMC_LP3_933_MR2,
		DMC_LP3_933_MR3,
		DMC_LP3_933_MR22,
		DMC_LP3_933_DTMG0,
		DMC_LP3_933_DTMG1,
		DMC_LP3_933_DTMG2,
		DMC_LP3_933_DTMG3,
		DMC_LP3_933_DTMG4,
		DMC_LP3_933_DTMG5,
		DMC_LP3_933_DTMG6,
		DMC_LP3_933_DTMG7,
		DMC_LP3_933_DTMG8,
		DMC_LP3_933_DTMG9,
		DMC_LP3_933_DTMG10,
		DMC_LP3_933_DTMG11,
		DMC_LP3_933_DTMG12,
		DMC_LP3_933_DTMG13,
		DMC_LP3_933_DTMG14,
		DMC_LP3_933_DTMG15,
		DMC_LP3_933_DTMG16,
		DMC_LP3_933_DTMG17,
		DMC_LP3_933_DTMG18,
		DMC_LP3_933_DTMG19,
	}
};

DDRC_DMC_DTMG_T dmc_tmg_lp4[]=
{
	{
		DMC_LP4_256_MR1,
		DMC_LP4_256_MR2,
		DMC_LP4_256_MR3,
		DMC_LP4_256_MR22,
		DMC_LP4_256_DTMG0,
		DMC_LP4_256_DTMG1,
		DMC_LP4_256_DTMG2,
		DMC_LP4_256_DTMG3,
		DMC_LP4_256_DTMG4,
		DMC_LP4_256_DTMG5,
		DMC_LP4_256_DTMG6,
		DMC_LP4_256_DTMG7,
		DMC_LP4_256_DTMG8,
		DMC_LP4_256_DTMG9,
		DMC_LP4_256_DTMG10,
		DMC_LP4_256_DTMG11,
		DMC_LP4_256_DTMG12,
		DMC_LP4_256_DTMG13,
		DMC_LP4_256_DTMG14,
		DMC_LP4_256_DTMG15,
		DMC_LP4_256_DTMG16,
		DMC_LP4_256_DTMG17,
		DMC_LP4_256_DTMG18,
		DMC_LP4_256_DTMG19,
	},
	{
		DMC_LP4_384_MR1,
		DMC_LP4_384_MR2,
		DMC_LP4_384_MR3,
		DMC_LP4_384_MR22,
		DMC_LP4_384_DTMG0,
		DMC_LP4_384_DTMG1,
		DMC_LP4_384_DTMG2,
		DMC_LP4_384_DTMG3,
		DMC_LP4_384_DTMG4,
		DMC_LP4_384_DTMG5,
		DMC_LP4_384_DTMG6,
		DMC_LP4_384_DTMG7,
		DMC_LP4_384_DTMG8,
		DMC_LP4_384_DTMG9,
		DMC_LP4_384_DTMG10,
		DMC_LP4_384_DTMG11,
		DMC_LP4_384_DTMG12,
		DMC_LP4_384_DTMG13,
		DMC_LP4_384_DTMG14,
		DMC_LP4_384_DTMG15,
		DMC_LP4_384_DTMG16,
		DMC_LP4_384_DTMG17,
		DMC_LP4_384_DTMG18,
		DMC_LP4_384_DTMG19,
	},
	{
		DMC_LP4_512_MR1,
		DMC_LP4_512_MR2,
		DMC_LP4_512_MR3,
		DMC_LP4_512_MR22,
		DMC_LP4_512_DTMG0,
		DMC_LP4_512_DTMG1,
		DMC_LP4_512_DTMG2,
		DMC_LP4_512_DTMG3,
		DMC_LP4_512_DTMG4,
		DMC_LP4_512_DTMG5,
		DMC_LP4_512_DTMG6,
		DMC_LP4_512_DTMG7,
		DMC_LP4_512_DTMG8,
		DMC_LP4_512_DTMG9,
		DMC_LP4_512_DTMG10,
		DMC_LP4_512_DTMG11,
		DMC_LP4_512_DTMG12,
		DMC_LP4_512_DTMG13,
		DMC_LP4_512_DTMG14,
		DMC_LP4_512_DTMG15,
		DMC_LP4_512_DTMG16,
		DMC_LP4_512_DTMG17,
		DMC_LP4_512_DTMG18,
		DMC_LP4_512_DTMG19,
	},
	{
		DMC_LP4_622_MR1,
		DMC_LP4_622_MR2,
		DMC_LP4_622_MR3,
		DMC_LP4_622_MR22,
		DMC_LP4_622_DTMG0,
		DMC_LP4_622_DTMG1,
		DMC_LP4_622_DTMG2,
		DMC_LP4_622_DTMG3,
		DMC_LP4_622_DTMG4,
		DMC_LP4_622_DTMG5,
		DMC_LP4_622_DTMG6,
		DMC_LP4_622_DTMG7,
		DMC_LP4_622_DTMG8,
		DMC_LP4_622_DTMG9,
		DMC_LP4_622_DTMG10,
		DMC_LP4_622_DTMG11,
		DMC_LP4_622_DTMG12,
		DMC_LP4_622_DTMG13,
		DMC_LP4_622_DTMG14,
		DMC_LP4_622_DTMG15,
		DMC_LP4_622_DTMG16,
		DMC_LP4_622_DTMG17,
		DMC_LP4_622_DTMG18,
		DMC_LP4_622_DTMG19,
	},
	{
		DMC_LP4_768_MR1,
		DMC_LP4_768_MR2,
		DMC_LP4_768_MR3,
		DMC_LP4_768_MR22,
		DMC_LP4_768_DTMG0,
		DMC_LP4_768_DTMG1,
		DMC_LP4_768_DTMG2,
		DMC_LP4_768_DTMG3,
		DMC_LP4_768_DTMG4,
		DMC_LP4_768_DTMG5,
		DMC_LP4_768_DTMG6,
		DMC_LP4_768_DTMG7,
		DMC_LP4_768_DTMG8,
		DMC_LP4_768_DTMG9,
		DMC_LP4_768_DTMG10,
		DMC_LP4_768_DTMG11,
		DMC_LP4_768_DTMG12,
		DMC_LP4_768_DTMG13,
		DMC_LP4_768_DTMG14,
		DMC_LP4_768_DTMG15,
		DMC_LP4_768_DTMG16,
		DMC_LP4_768_DTMG17,
		DMC_LP4_768_DTMG18,
		DMC_LP4_768_DTMG19,
	},
	{
		DMC_LP4_933_MR1,
		DMC_LP4_933_MR2,
		DMC_LP4_933_MR3,
		DMC_LP4_933_MR22,
		DMC_LP4_933_DTMG0,
		DMC_LP4_933_DTMG1,
		DMC_LP4_933_DTMG2,
		DMC_LP4_933_DTMG3,
		DMC_LP4_933_DTMG4,
		DMC_LP4_933_DTMG5,
		DMC_LP4_933_DTMG6,
		DMC_LP4_933_DTMG7,
		DMC_LP4_933_DTMG8,
		DMC_LP4_933_DTMG9,
		DMC_LP4_933_DTMG10,
		DMC_LP4_933_DTMG11,
		DMC_LP4_933_DTMG12,
		DMC_LP4_933_DTMG13,
		DMC_LP4_933_DTMG14,
		DMC_LP4_933_DTMG15,
		DMC_LP4_933_DTMG16,
		DMC_LP4_933_DTMG17,
		DMC_LP4_933_DTMG18,
		DMC_LP4_933_DTMG19,
	},
	{
		DMC_LP4_1200_MR1,
		DMC_LP4_1200_MR2,
		DMC_LP4_1200_MR3,
		DMC_LP4_1200_MR22,
		DMC_LP4_1200_DTMG0,
		DMC_LP4_1200_DTMG1,
		DMC_LP4_1200_DTMG2,
		DMC_LP4_1200_DTMG3,
		DMC_LP4_1200_DTMG4,
		DMC_LP4_1200_DTMG5,
		DMC_LP4_1200_DTMG6,
		DMC_LP4_1200_DTMG7,
		DMC_LP4_1200_DTMG8,
		DMC_LP4_1200_DTMG9,
		DMC_LP4_1200_DTMG10,
		DMC_LP4_1200_DTMG11,
		DMC_LP4_1200_DTMG12,
		DMC_LP4_1200_DTMG13,
		DMC_LP4_1200_DTMG14,
		DMC_LP4_1200_DTMG15,
		DMC_LP4_1200_DTMG16,
		DMC_LP4_1200_DTMG17,
		DMC_LP4_1200_DTMG18,
		DMC_LP4_1200_DTMG19,
	},
	{
		DMC_LP4_1333_MR1,
		DMC_LP4_1333_MR2,
		DMC_LP4_1333_MR3,
		DMC_LP4_1333_MR22,
		DMC_LP4_1333_DTMG0,
		DMC_LP4_1333_DTMG1,
		DMC_LP4_1333_DTMG2,
		DMC_LP4_1333_DTMG3,
		DMC_LP4_1333_DTMG4,
		DMC_LP4_1333_DTMG5,
		DMC_LP4_1333_DTMG6,
		DMC_LP4_1333_DTMG7,
		DMC_LP4_1333_DTMG8,
		DMC_LP4_1333_DTMG9,
		DMC_LP4_1333_DTMG10,
		DMC_LP4_1333_DTMG11,
		DMC_LP4_1333_DTMG12,
		DMC_LP4_1333_DTMG13,
		DMC_LP4_1333_DTMG14,
		DMC_LP4_1333_DTMG15,
		DMC_LP4_1333_DTMG16,
		DMC_LP4_1333_DTMG17,
		DMC_LP4_1333_DTMG18,
		DMC_LP4_1333_DTMG19,
	}
};


DDRC_PHY_TMG_T phy_tmg_lp3[]=
{
	{
		DDR_CLK_256M,
		DMC_PHY_LP3_256_TRAIN_EN,
		DMC_PHY_LP3_256_DTMG0,
		DMC_PHY_LP3_256_DTMG1,
		DMC_PHY_LP3_256_DTMG2,
		DMC_PHY_LP3_256_DTMG3,
		DMC_PHY_LP3_256_DTMG4,
		DMC_PHY_LP3_256_DTMG5,
		DMC_PHY_LP3_256_DTMG6,
		DMC_PHY_LP3_256_DTMG7,
		DMC_PHY_LP3_256_DTMG8,
		DMC_PHY_LP3_256_DTMG9,
		DMC_PHY_LP3_256_DTMG10,
		DMC_PHY_LP3_256_DTMG11,
		DMC_PHY_LP3_256_DTMG12,
		DMC_PHY_LP3_256_DTMG13,
		DMC_PHY_LP3_256_DTMG14,
		DMC_PHY_LP3_256_DTMG15,
		DMC_PHY_LP3_256_DTMG19,
		DMC_PHY_LP3_256_DTMG20,
		DMC_PHY_LP3_256_DTMG21,
		DMC_PHY_LP3_256_DTMG22,
		DMC_PHY_LP3_256_DTMG23,
		DMC_PHY_LP3_256_DTMG27,
		DMC_PHY_LP3_256_DTMG28,
		DMC_PHY_LP3_256_DTMG29,
		DMC_PHY_LP3_256_DTMG30,
		DMC_PHY_LP3_256_DTMG31,
		DMC_PHY_LP3_256_DTMG35,
		DMC_PHY_LP3_256_DTMG36,
		DMC_PHY_LP3_256_DTMG37,
		DMC_PHY_LP3_256_DTMG38,
		DMC_PHY_LP3_256_DTMG39,
		DMC_PHY_LP3_256_DTMG43,
		DMC_PHY_LP3_256_DTMG44,
		DMC_PHY_LP3_256_DTMG45,
	},
	{
		DDR_CLK_384M,
		DMC_PHY_LP3_384_TRAIN_EN,
		DMC_PHY_LP3_384_DTMG0,
		DMC_PHY_LP3_384_DTMG1,
		DMC_PHY_LP3_384_DTMG2,
		DMC_PHY_LP3_384_DTMG3,
		DMC_PHY_LP3_384_DTMG4,
		DMC_PHY_LP3_384_DTMG5,
		DMC_PHY_LP3_384_DTMG6,
		DMC_PHY_LP3_384_DTMG7,
		DMC_PHY_LP3_384_DTMG8,
		DMC_PHY_LP3_384_DTMG9,
		DMC_PHY_LP3_384_DTMG10,
		DMC_PHY_LP3_384_DTMG11,
		DMC_PHY_LP3_384_DTMG12,
		DMC_PHY_LP3_384_DTMG13,
		DMC_PHY_LP3_384_DTMG14,
		DMC_PHY_LP3_384_DTMG15,
		DMC_PHY_LP3_384_DTMG19,
		DMC_PHY_LP3_384_DTMG20,
		DMC_PHY_LP3_384_DTMG21,
		DMC_PHY_LP3_384_DTMG22,
		DMC_PHY_LP3_384_DTMG23,
		DMC_PHY_LP3_384_DTMG27,
		DMC_PHY_LP3_384_DTMG28,
		DMC_PHY_LP3_384_DTMG29,
		DMC_PHY_LP3_384_DTMG30,
		DMC_PHY_LP3_384_DTMG31,
		DMC_PHY_LP3_384_DTMG35,
		DMC_PHY_LP3_384_DTMG36,
		DMC_PHY_LP3_384_DTMG37,
		DMC_PHY_LP3_384_DTMG38,
		DMC_PHY_LP3_384_DTMG39,
		DMC_PHY_LP3_384_DTMG43,
		DMC_PHY_LP3_384_DTMG44,
		DMC_PHY_LP3_384_DTMG45,
	},
	{
		DDR_CLK_512M,
		DMC_PHY_LP3_512_TRAIN_EN,
		DMC_PHY_LP3_512_DTMG0,
		DMC_PHY_LP3_512_DTMG1,
		DMC_PHY_LP3_512_DTMG2,
		DMC_PHY_LP3_512_DTMG3,
		DMC_PHY_LP3_512_DTMG4,
		DMC_PHY_LP3_512_DTMG5,
		DMC_PHY_LP3_512_DTMG6,
		DMC_PHY_LP3_512_DTMG7,
		DMC_PHY_LP3_512_DTMG8,
		DMC_PHY_LP3_512_DTMG9,
		DMC_PHY_LP3_512_DTMG10,
		DMC_PHY_LP3_512_DTMG11,
		DMC_PHY_LP3_512_DTMG12,
		DMC_PHY_LP3_512_DTMG13,
		DMC_PHY_LP3_512_DTMG14,
		DMC_PHY_LP3_512_DTMG15,
		DMC_PHY_LP3_512_DTMG19,
		DMC_PHY_LP3_512_DTMG20,
		DMC_PHY_LP3_512_DTMG21,
		DMC_PHY_LP3_512_DTMG22,
		DMC_PHY_LP3_512_DTMG23,
		DMC_PHY_LP3_512_DTMG27,
		DMC_PHY_LP3_512_DTMG28,
		DMC_PHY_LP3_512_DTMG29,
		DMC_PHY_LP3_512_DTMG30,
		DMC_PHY_LP3_512_DTMG31,
		DMC_PHY_LP3_512_DTMG35,
		DMC_PHY_LP3_512_DTMG36,
		DMC_PHY_LP3_512_DTMG37,
		DMC_PHY_LP3_512_DTMG38,
		DMC_PHY_LP3_512_DTMG39,
		DMC_PHY_LP3_512_DTMG43,
		DMC_PHY_LP3_512_DTMG44,
		DMC_PHY_LP3_512_DTMG45,
	},
	{
		DDR_CLK_622M,
		DMC_PHY_LP3_622_TRAIN_EN,
		DMC_PHY_LP3_622_DTMG0,
		DMC_PHY_LP3_622_DTMG1,
		DMC_PHY_LP3_622_DTMG2,
		DMC_PHY_LP3_622_DTMG3,
		DMC_PHY_LP3_622_DTMG4,
		DMC_PHY_LP3_622_DTMG5,
		DMC_PHY_LP3_622_DTMG6,
		DMC_PHY_LP3_622_DTMG7,
		DMC_PHY_LP3_622_DTMG8,
		DMC_PHY_LP3_622_DTMG9,
		DMC_PHY_LP3_622_DTMG10,
		DMC_PHY_LP3_622_DTMG11,
		DMC_PHY_LP3_622_DTMG12,
		DMC_PHY_LP3_622_DTMG13,
		DMC_PHY_LP3_622_DTMG14,
		DMC_PHY_LP3_622_DTMG15,
		DMC_PHY_LP3_622_DTMG19,
		DMC_PHY_LP3_622_DTMG20,
		DMC_PHY_LP3_622_DTMG21,
		DMC_PHY_LP3_622_DTMG22,
		DMC_PHY_LP3_622_DTMG23,
		DMC_PHY_LP3_622_DTMG27,
		DMC_PHY_LP3_622_DTMG28,
		DMC_PHY_LP3_622_DTMG29,
		DMC_PHY_LP3_622_DTMG30,
		DMC_PHY_LP3_622_DTMG31,
		DMC_PHY_LP3_622_DTMG35,
		DMC_PHY_LP3_622_DTMG36,
		DMC_PHY_LP3_622_DTMG37,
		DMC_PHY_LP3_622_DTMG38,
		DMC_PHY_LP3_622_DTMG39,
		DMC_PHY_LP3_622_DTMG43,
		DMC_PHY_LP3_622_DTMG44,
		DMC_PHY_LP3_622_DTMG45,
	},
	{
		DDR_CLK_768M,
		DMC_PHY_LP3_768_TRAIN_EN,
		DMC_PHY_LP3_768_DTMG0,
		DMC_PHY_LP3_768_DTMG1,
		DMC_PHY_LP3_768_DTMG2,
		DMC_PHY_LP3_768_DTMG3,
		DMC_PHY_LP3_768_DTMG4,
		DMC_PHY_LP3_768_DTMG5,
		DMC_PHY_LP3_768_DTMG6,
		DMC_PHY_LP3_768_DTMG7,
		DMC_PHY_LP3_768_DTMG8,
		DMC_PHY_LP3_768_DTMG9,
		DMC_PHY_LP3_768_DTMG10,
		DMC_PHY_LP3_768_DTMG11,
		DMC_PHY_LP3_768_DTMG12,
		DMC_PHY_LP3_768_DTMG13,
		DMC_PHY_LP3_768_DTMG14,
		DMC_PHY_LP3_768_DTMG15,
		DMC_PHY_LP3_768_DTMG19,
		DMC_PHY_LP3_768_DTMG20,
		DMC_PHY_LP3_768_DTMG21,
		DMC_PHY_LP3_768_DTMG22,
		DMC_PHY_LP3_768_DTMG23,
		DMC_PHY_LP3_768_DTMG27,
		DMC_PHY_LP3_768_DTMG28,
		DMC_PHY_LP3_768_DTMG29,
		DMC_PHY_LP3_768_DTMG30,
		DMC_PHY_LP3_768_DTMG31,
		DMC_PHY_LP3_768_DTMG35,
		DMC_PHY_LP3_768_DTMG36,
		DMC_PHY_LP3_768_DTMG37,
		DMC_PHY_LP3_768_DTMG38,
		DMC_PHY_LP3_768_DTMG39,
		DMC_PHY_LP3_768_DTMG43,
		DMC_PHY_LP3_768_DTMG44,
		DMC_PHY_LP3_768_DTMG45,
	},
	{
		DDR_CLK_933M,
		DMC_PHY_LP3_933_TRAIN_EN,
		DMC_PHY_LP3_933_DTMG0,
		DMC_PHY_LP3_933_DTMG1,
		DMC_PHY_LP3_933_DTMG2,
		DMC_PHY_LP3_933_DTMG3,
		DMC_PHY_LP3_933_DTMG4,
		DMC_PHY_LP3_933_DTMG5,
		DMC_PHY_LP3_933_DTMG6,
		DMC_PHY_LP3_933_DTMG7,
		DMC_PHY_LP3_933_DTMG8,
		DMC_PHY_LP3_933_DTMG9,
		DMC_PHY_LP3_933_DTMG10,
		DMC_PHY_LP3_933_DTMG11,
		DMC_PHY_LP3_933_DTMG12,
		DMC_PHY_LP3_933_DTMG13,
		DMC_PHY_LP3_933_DTMG14,
		DMC_PHY_LP3_933_DTMG15,
		DMC_PHY_LP3_933_DTMG19,
		DMC_PHY_LP3_933_DTMG20,
		DMC_PHY_LP3_933_DTMG21,
		DMC_PHY_LP3_933_DTMG22,
		DMC_PHY_LP3_933_DTMG23,
		DMC_PHY_LP3_933_DTMG27,
		DMC_PHY_LP3_933_DTMG28,
		DMC_PHY_LP3_933_DTMG29,
		DMC_PHY_LP3_933_DTMG30,
		DMC_PHY_LP3_933_DTMG31,
		DMC_PHY_LP3_933_DTMG35,
		DMC_PHY_LP3_933_DTMG36,
		DMC_PHY_LP3_933_DTMG37,
		DMC_PHY_LP3_933_DTMG38,
		DMC_PHY_LP3_933_DTMG39,
		DMC_PHY_LP3_933_DTMG43,
		DMC_PHY_LP3_933_DTMG44,
		DMC_PHY_LP3_933_DTMG45,
	}
};


DDRC_PHY_TMG_T phy_tmg_lp4[]=
{
	{
		DDR_CLK_256M,
		DMC_PHY_LP4_256_TRAIN_EN,
		DMC_PHY_LP4_256_DTMG0,
		DMC_PHY_LP4_256_DTMG1,
		DMC_PHY_LP4_256_DTMG2,
		DMC_PHY_LP4_256_DTMG3,
		DMC_PHY_LP4_256_DTMG4,
		DMC_PHY_LP4_256_DTMG5,
		DMC_PHY_LP4_256_DTMG6,
		DMC_PHY_LP4_256_DTMG7,
		DMC_PHY_LP4_256_DTMG8,
		DMC_PHY_LP4_256_DTMG9,
		DMC_PHY_LP4_256_DTMG10,
		DMC_PHY_LP4_256_DTMG11,
		DMC_PHY_LP4_256_DTMG12,
		DMC_PHY_LP4_256_DTMG13,
		DMC_PHY_LP4_256_DTMG14,
		DMC_PHY_LP4_256_DTMG15,
		DMC_PHY_LP4_256_DTMG19,
		DMC_PHY_LP4_256_DTMG20,
		DMC_PHY_LP4_256_DTMG21,
		DMC_PHY_LP4_256_DTMG22,
		DMC_PHY_LP4_256_DTMG23,
		DMC_PHY_LP4_256_DTMG27,
		DMC_PHY_LP4_256_DTMG28,
		DMC_PHY_LP4_256_DTMG29,
		DMC_PHY_LP4_256_DTMG30,
		DMC_PHY_LP4_256_DTMG31,
		DMC_PHY_LP4_256_DTMG35,
		DMC_PHY_LP4_256_DTMG36,
		DMC_PHY_LP4_256_DTMG37,
		DMC_PHY_LP4_256_DTMG38,
		DMC_PHY_LP4_256_DTMG39,
		DMC_PHY_LP4_256_DTMG43,
		DMC_PHY_LP4_256_DTMG44,
		DMC_PHY_LP4_256_DTMG45,
	},
	{
		DDR_CLK_384M,
		DMC_PHY_LP4_384_TRAIN_EN,
		DMC_PHY_LP4_384_DTMG0,
		DMC_PHY_LP4_384_DTMG1,
		DMC_PHY_LP4_384_DTMG2,
		DMC_PHY_LP4_384_DTMG3,
		DMC_PHY_LP4_384_DTMG4,
		DMC_PHY_LP4_384_DTMG5,
		DMC_PHY_LP4_384_DTMG6,
		DMC_PHY_LP4_384_DTMG7,
		DMC_PHY_LP4_384_DTMG8,
		DMC_PHY_LP4_384_DTMG9,
		DMC_PHY_LP4_384_DTMG10,
		DMC_PHY_LP4_384_DTMG11,
		DMC_PHY_LP4_384_DTMG12,
		DMC_PHY_LP4_384_DTMG13,
		DMC_PHY_LP4_384_DTMG14,
		DMC_PHY_LP4_384_DTMG15,
		DMC_PHY_LP4_384_DTMG19,
		DMC_PHY_LP4_384_DTMG20,
		DMC_PHY_LP4_384_DTMG21,
		DMC_PHY_LP4_384_DTMG22,
		DMC_PHY_LP4_384_DTMG23,
		DMC_PHY_LP4_384_DTMG27,
		DMC_PHY_LP4_384_DTMG28,
		DMC_PHY_LP4_384_DTMG29,
		DMC_PHY_LP4_384_DTMG30,
		DMC_PHY_LP4_384_DTMG31,
		DMC_PHY_LP4_384_DTMG35,
		DMC_PHY_LP4_384_DTMG36,
		DMC_PHY_LP4_384_DTMG37,
		DMC_PHY_LP4_384_DTMG38,
		DMC_PHY_LP4_384_DTMG39,
		DMC_PHY_LP4_384_DTMG43,
		DMC_PHY_LP4_384_DTMG44,
		DMC_PHY_LP4_384_DTMG45,
	},
	{
		DDR_CLK_512M,
		DMC_PHY_LP4_512_TRAIN_EN,
		DMC_PHY_LP4_512_DTMG0,
		DMC_PHY_LP4_512_DTMG1,
		DMC_PHY_LP4_512_DTMG2,
		DMC_PHY_LP4_512_DTMG3,
		DMC_PHY_LP4_512_DTMG4,
		DMC_PHY_LP4_512_DTMG5,
		DMC_PHY_LP4_512_DTMG6,
		DMC_PHY_LP4_512_DTMG7,
		DMC_PHY_LP4_512_DTMG8,
		DMC_PHY_LP4_512_DTMG9,
		DMC_PHY_LP4_512_DTMG10,
		DMC_PHY_LP4_512_DTMG11,
		DMC_PHY_LP4_512_DTMG12,
		DMC_PHY_LP4_512_DTMG13,
		DMC_PHY_LP4_512_DTMG14,
		DMC_PHY_LP4_512_DTMG15,
		DMC_PHY_LP4_512_DTMG19,
		DMC_PHY_LP4_512_DTMG20,
		DMC_PHY_LP4_512_DTMG21,
		DMC_PHY_LP4_512_DTMG22,
		DMC_PHY_LP4_512_DTMG23,
		DMC_PHY_LP4_512_DTMG27,
		DMC_PHY_LP4_512_DTMG28,
		DMC_PHY_LP4_512_DTMG29,
		DMC_PHY_LP4_512_DTMG30,
		DMC_PHY_LP4_512_DTMG31,
		DMC_PHY_LP4_512_DTMG35,
		DMC_PHY_LP4_512_DTMG36,
		DMC_PHY_LP4_512_DTMG37,
		DMC_PHY_LP4_512_DTMG38,
		DMC_PHY_LP4_512_DTMG39,
		DMC_PHY_LP4_512_DTMG43,
		DMC_PHY_LP4_512_DTMG44,
		DMC_PHY_LP4_512_DTMG45,
	},
	{
		DDR_CLK_622M,
		DMC_PHY_LP4_622_TRAIN_EN,
		DMC_PHY_LP4_622_DTMG0,
		DMC_PHY_LP4_622_DTMG1,
		DMC_PHY_LP4_622_DTMG2,
		DMC_PHY_LP4_622_DTMG3,
		DMC_PHY_LP4_622_DTMG4,
		DMC_PHY_LP4_622_DTMG5,
		DMC_PHY_LP4_622_DTMG6,
		DMC_PHY_LP4_622_DTMG7,
		DMC_PHY_LP4_622_DTMG8,
		DMC_PHY_LP4_622_DTMG9,
		DMC_PHY_LP4_622_DTMG10,
		DMC_PHY_LP4_622_DTMG11,
		DMC_PHY_LP4_622_DTMG12,
		DMC_PHY_LP4_622_DTMG13,
		DMC_PHY_LP4_622_DTMG14,
		DMC_PHY_LP4_622_DTMG15,
		DMC_PHY_LP4_622_DTMG19,
		DMC_PHY_LP4_622_DTMG20,
		DMC_PHY_LP4_622_DTMG21,
		DMC_PHY_LP4_622_DTMG22,
		DMC_PHY_LP4_622_DTMG23,
		DMC_PHY_LP4_622_DTMG27,
		DMC_PHY_LP4_622_DTMG28,
		DMC_PHY_LP4_622_DTMG29,
		DMC_PHY_LP4_622_DTMG30,
		DMC_PHY_LP4_622_DTMG31,
		DMC_PHY_LP4_622_DTMG35,
		DMC_PHY_LP4_622_DTMG36,
		DMC_PHY_LP4_622_DTMG37,
		DMC_PHY_LP4_622_DTMG38,
		DMC_PHY_LP4_622_DTMG39,
		DMC_PHY_LP4_622_DTMG43,
		DMC_PHY_LP4_622_DTMG44,
		DMC_PHY_LP4_622_DTMG45,
	},
	{
		DDR_CLK_768M,
		DMC_PHY_LP4_768_TRAIN_EN,
		DMC_PHY_LP4_768_DTMG0,
		DMC_PHY_LP4_768_DTMG1,
		DMC_PHY_LP4_768_DTMG2,
		DMC_PHY_LP4_768_DTMG3,
		DMC_PHY_LP4_768_DTMG4,
		DMC_PHY_LP4_768_DTMG5,
		DMC_PHY_LP4_768_DTMG6,
		DMC_PHY_LP4_768_DTMG7,
		DMC_PHY_LP4_768_DTMG8,
		DMC_PHY_LP4_768_DTMG9,
		DMC_PHY_LP4_768_DTMG10,
		DMC_PHY_LP4_768_DTMG11,
		DMC_PHY_LP4_768_DTMG12,
		DMC_PHY_LP4_768_DTMG13,
		DMC_PHY_LP4_768_DTMG14,
		DMC_PHY_LP4_768_DTMG15,
		DMC_PHY_LP4_768_DTMG19,
		DMC_PHY_LP4_768_DTMG20,
		DMC_PHY_LP4_768_DTMG21,
		DMC_PHY_LP4_768_DTMG22,
		DMC_PHY_LP4_768_DTMG23,
		DMC_PHY_LP4_768_DTMG27,
		DMC_PHY_LP4_768_DTMG28,
		DMC_PHY_LP4_768_DTMG29,
		DMC_PHY_LP4_768_DTMG30,
		DMC_PHY_LP4_768_DTMG31,
		DMC_PHY_LP4_768_DTMG35,
		DMC_PHY_LP4_768_DTMG36,
		DMC_PHY_LP4_768_DTMG37,
		DMC_PHY_LP4_768_DTMG38,
		DMC_PHY_LP4_768_DTMG39,
		DMC_PHY_LP4_768_DTMG43,
		DMC_PHY_LP4_768_DTMG44,
		DMC_PHY_LP4_768_DTMG45,
	},
	{
		DDR_CLK_933M,
		DMC_PHY_LP4_933_TRAIN_EN,
		DMC_PHY_LP4_933_DTMG0,
		DMC_PHY_LP4_933_DTMG1,
		DMC_PHY_LP4_933_DTMG2,
		DMC_PHY_LP4_933_DTMG3,
		DMC_PHY_LP4_933_DTMG4,
		DMC_PHY_LP4_933_DTMG5,
		DMC_PHY_LP4_933_DTMG6,
		DMC_PHY_LP4_933_DTMG7,
		DMC_PHY_LP4_933_DTMG8,
		DMC_PHY_LP4_933_DTMG9,
		DMC_PHY_LP4_933_DTMG10,
		DMC_PHY_LP4_933_DTMG11,
		DMC_PHY_LP4_933_DTMG12,
		DMC_PHY_LP4_933_DTMG13,
		DMC_PHY_LP4_933_DTMG14,
		DMC_PHY_LP4_933_DTMG15,
		DMC_PHY_LP4_933_DTMG19,
		DMC_PHY_LP4_933_DTMG20,
		DMC_PHY_LP4_933_DTMG21,
		DMC_PHY_LP4_933_DTMG22,
		DMC_PHY_LP4_933_DTMG23,
		DMC_PHY_LP4_933_DTMG27,
		DMC_PHY_LP4_933_DTMG28,
		DMC_PHY_LP4_933_DTMG29,
		DMC_PHY_LP4_933_DTMG30,
		DMC_PHY_LP4_933_DTMG31,
		DMC_PHY_LP4_933_DTMG35,
		DMC_PHY_LP4_933_DTMG36,
		DMC_PHY_LP4_933_DTMG37,
		DMC_PHY_LP4_933_DTMG38,
		DMC_PHY_LP4_933_DTMG39,
		DMC_PHY_LP4_933_DTMG43,
		DMC_PHY_LP4_933_DTMG44,
		DMC_PHY_LP4_933_DTMG45,
	},
	{
		DDR_CLK_1200M,
		DMC_PHY_LP4_1200_TRAIN_EN,
		DMC_PHY_LP4_1200_DTMG0,
		DMC_PHY_LP4_1200_DTMG1,
		DMC_PHY_LP4_1200_DTMG2,
		DMC_PHY_LP4_1200_DTMG3,
		DMC_PHY_LP4_1200_DTMG4,
		DMC_PHY_LP4_1200_DTMG5,
		DMC_PHY_LP4_1200_DTMG6,
		DMC_PHY_LP4_1200_DTMG7,
		DMC_PHY_LP4_1200_DTMG8,
		DMC_PHY_LP4_1200_DTMG9,
		DMC_PHY_LP4_1200_DTMG10,
		DMC_PHY_LP4_1200_DTMG11,
		DMC_PHY_LP4_1200_DTMG12,
		DMC_PHY_LP4_1200_DTMG13,
		DMC_PHY_LP4_1200_DTMG14,
		DMC_PHY_LP4_1200_DTMG15,
		DMC_PHY_LP4_1200_DTMG19,
		DMC_PHY_LP4_1200_DTMG20,
		DMC_PHY_LP4_1200_DTMG21,
		DMC_PHY_LP4_1200_DTMG22,
		DMC_PHY_LP4_1200_DTMG23,
		DMC_PHY_LP4_1200_DTMG27,
		DMC_PHY_LP4_1200_DTMG28,
		DMC_PHY_LP4_1200_DTMG29,
		DMC_PHY_LP4_1200_DTMG30,
		DMC_PHY_LP4_1200_DTMG31,
		DMC_PHY_LP4_1200_DTMG35,
		DMC_PHY_LP4_1200_DTMG36,
		DMC_PHY_LP4_1200_DTMG37,
		DMC_PHY_LP4_1200_DTMG38,
		DMC_PHY_LP4_1200_DTMG39,
		DMC_PHY_LP4_1200_DTMG43,
		DMC_PHY_LP4_1200_DTMG44,
		DMC_PHY_LP4_1200_DTMG45,
	},
	{
		DDR_CLK_1333M,
		DMC_PHY_LP4_1333_TRAIN_EN,
		DMC_PHY_LP4_1333_DTMG0,
		DMC_PHY_LP4_1333_DTMG1,
		DMC_PHY_LP4_1333_DTMG2,
		DMC_PHY_LP4_1333_DTMG3,
		DMC_PHY_LP4_1333_DTMG4,
		DMC_PHY_LP4_1333_DTMG5,
		DMC_PHY_LP4_1333_DTMG6,
		DMC_PHY_LP4_1333_DTMG7,
		DMC_PHY_LP4_1333_DTMG8,
		DMC_PHY_LP4_1333_DTMG9,
		DMC_PHY_LP4_1333_DTMG10,
		DMC_PHY_LP4_1333_DTMG11,
		DMC_PHY_LP4_1333_DTMG12,
		DMC_PHY_LP4_1333_DTMG13,
		DMC_PHY_LP4_1333_DTMG14,
		DMC_PHY_LP4_1333_DTMG15,
		DMC_PHY_LP4_1333_DTMG19,
		DMC_PHY_LP4_1333_DTMG20,
		DMC_PHY_LP4_1333_DTMG21,
		DMC_PHY_LP4_1333_DTMG22,
		DMC_PHY_LP4_1333_DTMG23,
		DMC_PHY_LP4_1333_DTMG27,
		DMC_PHY_LP4_1333_DTMG28,
		DMC_PHY_LP4_1333_DTMG29,
		DMC_PHY_LP4_1333_DTMG30,
		DMC_PHY_LP4_1333_DTMG31,
		DMC_PHY_LP4_1333_DTMG35,
		DMC_PHY_LP4_1333_DTMG36,
		DMC_PHY_LP4_1333_DTMG37,
		DMC_PHY_LP4_1333_DTMG38,
		DMC_PHY_LP4_1333_DTMG39,
		DMC_PHY_LP4_1333_DTMG43,
		DMC_PHY_LP4_1333_DTMG44,
		DMC_PHY_LP4_1333_DTMG45,
	},
};

/*
*1)DDR_CLK
*2)DDR_FREQ_NUM
*3)PUB_DFS_SW_RATIO:
*  bit[2:0]:clock source select:000-DPLL0/111-TWPLL/1536M
*  bit[6:3]:DPLL0 div value=N+1
*4)PUB_DFS_SW_CLK_MODE:
*  00-pure bypass mode/01-deskewpll mode/10-deskewdll mode
*5)PUB_DFS_SW_RATIO_D2:
*  bit[1:0]:clk_x1_d2
*			0-div0/1-div2/2-div4
*  bit[3:2]:clk_d2_select
*			0-div0/1-div2/2-div4
*6)HALF_FREQ_MODE:dmc_clk:phy_clk
*					0-1:2/1-1:1
*/
DDRC_FREQ_INFO_T ddrc_freq_info[]=
{
	{DDR_CLK_256M,	0,	0x44,	0x0,	0x9,	0x1},
	{DDR_CLK_384M,	1,	0x45,	0x0,	0x9,	0x1},
	{DDR_CLK_512M,	2,	0x44,	0x1,	0x4,	0x1},
	{DDR_CLK_622M,	3,	0x28,	0x1,	0x0,	0x0},
	{DDR_CLK_768M,	4,	0x43,	0x1,	0x0,	0x0},
	{DDR_CLK_933M,	5,	0x18,	0x1,	0x0,	0x0},
	{DDR_CLK_1200M,	6,	0x08,	0x1,	0x0,	0x0},
	{DDR_CLK_1333M,	7,	0x08,	0x1,	0x0,	0x0},
};

/*
*bit[9:0]:tXSR
*bit[23:16]:tRFCpb
*bit[31:24]:tRFC
*/
u32 lp3_size_timing[2][6] =
{
	{0x10070012,0x180b001b,0x210e0024,0x3812002c,0x31160036,0x3c1b0042},
	{0x1a0b001d,0x2810002b,0x35160039,0x411b0045,0x50220055,0x61290067}
};

#if defined(VRCG_ON_EN)
u32 lp4_size_timing[4][8] =
{
	{0x1007003a,0x180b004a,0x210e005a,0x28120068,0x3116007d,0x3c1b0095,0x4d2300bc,0x562700d0},
	{0x170b003a,0x2210004a,0x2e16005a,0x371b0068,0x4522007d,0x53290095,0x6b3500bc,0x773b00d0},
	{0x2311003a,0x351a004a,0x4723005a,0x572b0068,0x6b35007d,0x82400095,0xa75300bc,0xba5c00d0},
	{0x3017003a,0x4823004d,0x61300066,0x763a007b,0x91480097,0xb15800b7,0xe37100eb,0xfd7e0105}
};
#else
u32 lp4_size_timing[4][8] =
{
	{0x10070012,0x180b001b,0x210e0024,0x2812002b,0x31160035,0x3c1b0041,0x4d230053,0x56270126},
	{0x170b0018,0x22100024,0x2e160030,0x371b003b,0x45220048,0x53290058,0x6b350071,0x773b0126},
	{0x23110025,0x351a0038,0x4723004a,0x572b005a,0x6b35006f,0x82400087,0xa75300ad,0xba5c0126},
	{0x30170032,0x4823004b,0x61300064,0x763a0079,0x91480095,0xb15800b9,0xe37100e9,0xfd7e0126}
};
#endif

